There is a growing need for high performance low power circuits in areas such as on-chip interconnect and globally asynchronous locally synchronous (“GALS”) systems. Many template-based asynchronous circuits fulfill these needs but are not easily accepted by designers due to a lack of support by commercial CAD tools, including in particular, timing sign-off.
Previous approached using relative timing (“RT”) have been introduced for modeling and verifying circuits that have timing constraints that must be satisfied to guarantee correct operation. Relative timing is premised on the observation that timing correctness typically depends on enforcing a relative ordering between signals that can and should be explicitly identified and verified. Coupled with absolute margins, such RT constraints should be adhered to during synthesis and P&R and then verified post-layout. Previous work in RT has presented various approaches for using the relative timing approach during synthesis and verification of asynchronous systems. However, the connection between relative timing and post-layout sign-off using static timing analysis has yet to be addressed.
Some previous techniques have applied static timing analysis (“STA”) tools in desynchronization. One such technique includes a fully-automated flow from synthesis to place and route in which an asynchronous design is produced from a synchronous Verilog netlist by replacing each flip-flop with two latches and the clock with handshaking control signals coupled with run-time-configurable matched delay lines. As part of such flow, STA is used to verify correct timing in the specific semi-decoupled four-phase controllers used, but such a technique fails to provide an extension to template-based circuit design. In addition, the verification is not based on relative timing but rather on max-delay constraints with absolute metrics, which can lead to false negatives. Virtual clocks are added to the design to model the datapath as a conventional master-slave latch-based design with non-overlapping clocks. This guarantees that the latency of the combinational logic is constrained and that the associated delay-lines will be sufficiently long.
What is needed therefore are new techniques that provide for improved and effective timing and power characterization flows for asynchronous circuits.